1. Technical Field
The present invention relates to a system and method for a high frequency stall design. More particularly, the present invention relates to a system and method for controlling instruction issuance to a backend pipeline in a high frequency, deeply pipelined system.
2. Description of the Related Art
Computer system designs incorporate a multitude of design approaches in order to achieve maximum performance. Once such design approach is pipelining. A pipeline is an implementation technique whereby multiple instructions are overlapped in execution. Without a pipeline, a processor fetches an instruction from memory, performs the operation corresponding to the instruction, and then fetches another instruction. Using a non-pipelined approach, the processor's arithmetic units are idle when the processor fetches instructions.
With pipelining, however, the computer system fetches instructions and stages them in a buffer while the processor performs arithmetic operations. Fetching and staging instructions is continuous, which results is an increase in the number of instructions that may be performed during a given time period.
Computer processor pipelining is typically divided into a front-end pipeline and a backend pipeline. The front-end pipeline includes instruction units, such as a fetch unit and an issue unit. The backend pipeline includes execution units, such as a fixed-point unit and a floating-point unit. The front-end pipeline's issue unit typically includes issue control logic for controlling instruction issuance to the backend pipeline.
A challenge found is that in high frequency, deeply-pipelined designs, implementing the issue control logic in order to meet timing constraints is extremely difficult because it requires decision feedback from a previous instruction cycle. In addition, the issue control logic complexity increases when the backend pipeline includes a multitude of execution units, each with varying restrictions and rules that the issue control logic follows.
Furthermore, the issue control logic design complexity multiplies for dual-issue systems. A dual-issue system allows two instructions to flow through the pipeline and issue simultaneously, barring any resource conflicts. In low Fan Out 4 (FO4) designs, such as 10FO4 to 16FO4, a dual-issue processor requires extremely efficient issue control logic in order to effectively control high frequency operation.
What is needed, therefore, is a system and method that controls instruction issuance in a high-frequency, deeply pipelined design in a very efficient manner in order to meet low FO4 design considerations.